In a floating gate non-volatile memory cell, where typically polysilicon is used as charge storage medium, a dielectric is known as an interpoly dielectric (IPD). The conventional interpoly dielectrics of non-volatile memory cells are based on SiO2/Si3N4/SiO2 (ONO) stacks which may lack scalability to below 10 nm equivalent oxide thickness (EOT). When a high-k dielectric material is used in an interpoly dielectric of a floating gate memory, care may need to be taken to avoid forming a lower-k material (e.g., SiO2) in between the layer of high-k material and the silicon floating gate. This bottom layer of lower-k material has a dielectric constant which is lower than that of the upper layer of high-k material. The combination of a lower-k/higher-k layer stack may unintentionally create a so-called Variot effect, an effect discussed in EP-A-1253646.
When present, the Variot effect may reduce the ability of a non-volatile memory to achieve a sufficiently large shift in threshold voltage, Vt, level when injecting carriers into the charge storage gate during programming, due to parasitic charge leakage through the interpoly dielectric. As a consequence, the threshold Vt-window may not be sufficient to ensure multilevel cell operation.